10 Sep

Wafer Smart Cut Technology

Wafer Smart Technology

Smart technology is a method which has been developed since 1993. It really is based on the direct bonding of two wafers, certainly one of that has first been implanted by light gas ions, with splitting induced in the implanted zone.

Implantation of ions, such as for instance hydrogen or helium, contributes to the formation of a weakened buried zone, located during the mean depth of ion penetration. Following the implanted wafer is bonded to a second wafer, splitting may occur, for which a thin layer is transferred from the implanted wafer onto the second wafer. Comparable scenarios occur as soon as the second wafer is replaced by a thick layer stiff adequate to allow splitting.

Semiconductor testing for Wafer Smart Technology was initially developed for Solar Projects and then it was later adapted for wafer applications. It really is now mature adequate to allow industrial-volume production of high-quality SOI wafers. The Smart process for producing SOI wafers is composed of listed here steps:

• A first Si wafer is thermally oxidized.

• Ions (H, He, etc.) are implanted in this first oxidized wafer to induce a buried weak zone.

• The first implanted wafer will be cleaned and directly bonded to an extra support wafer.

• Splitting is induced when you look at the weakened zone, transferring a thin layer from the first implanted wafer to your second support wafer.

• A final stage of treatment removes the roughness left in the surfaces after splitting, resulting in the last SOI structure. This enables the rest of the the main donor wafer to be reclaimed.

Fourier transform infrared spectroscopy operated in a multiple internal reflection mode, FTIR-MIR, enables the character of bonds and their densities in the bonding interface to be measured. Thermally grown oxide layers are 10 nm thick.65 Figure 1.16 shows clearly that –OH band peaks, into the 3000–3700 cm− 1 wave number range, are strongly modified at annealing temperatures over 250 °C. Water peaks, located into the 3200–3500 cm− 1 range, decrease continuously. Si–OH peaks into the 3500–3700 cm− 1 range first increase with temperature, up to 350 °C, and then decrease for higher temperatures.

Direct bonding, which occurs in the nanometer scale, is induced by hydrogen bonds either via water molecules adsorbed on silanol groups (Si–OH) or between silanols through the two surfaces. So, an initial approach is to increase silanol density and, specifically, water diffusion into the oxide subsurface. A surface preparation process such as for instance CMP in a basic solution (pH within the selection of 9–11) is well suited to induce these changes.

10 Sep

Wafer Probing with Automatic Test Equipment

The electrical test utilized by probing is almost certainly not as extensive as production electrical testing at post-assembly device level. Nonetheless, probing needs to be in a position to check if the dice on a wafer are functional and meeting critical electrical parameters. Good probing systems can map the failing dice on a wafer, relating the positioning associated with die from the wafer to the failure modes observed.

Examples of ATE (Automated Test Equipment) Interfaces for Probe Systems

Automatic Test Equipment (ATE) use is an expensive process, so it’s usually dispensed with for mature and stable items that are able to meet yield expectations despite blind assembly.

Laser diode wafer trimming is the method of adjusting the resistance worth of a laser diode wafer from the die, and it is attained by burning ‘notches’ in the laser diode wafer structure using a laser beam. Cutting across a laser diode with a laser beam reduces the laser diode’s effective cross-section, enhancing the resistance value. laser diode trimming is a fine-tuning step done to optimize the parametric characteristics of a tool.

No matter what application – device characterization, modeling, process development, design de-bug or IC failure analysis, Cascade 200 mm wafer probing systems have the precision and versatility needed for the essential advanced semiconductor processes and aggressively scaled devices.

Laser diode trimming is usually done in conjunction with wafer probing, wherein an electrical parameter measured during probing is defined within the acceptable range by adjusting the resistance value of the appropriate laser diode.